Solid-state imaging device

ABSTRACT

In a solid-state imaging device, a first substrate has a plurality of pixels and a plurality of first control signal lines. The plurality of first control signal lines are connected to pixels of each row. The second substrate includes a plurality of second control signal lines and a control circuit. The arrangement of each of the plurality of second control signal lines on the second substrate corresponds to the arrangement of a corresponding one of the plurality of first control signal lines on the first substrate. The connection portion has a plurality of control connections and a plurality of readout connections. Each of the plurality of control connections is connected to one of the plurality of first control signal lines and a corresponding one of the plurality of second control signal lines.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a solid-state imaging device.

This application is a continuation application based on InternationalPatent Application No. PCT/JP2015/059087, filed Mar. 25, 2015, and thecontent thereof is incorporated herein by reference.

Description of Related Art

Japanese Patent Application Publication, First Publication No.2013-90127 discloses a technology for miniaturizing a solid-stateimaging device. The solid-state imaging device disclosed in JapanesePatent Application Publication, First Publication No. 2013-90127 has aplurality of laminated substrates on which pixels and other circuits aredistributed. Demand for miniaturization of electronic devices requiresfurther miniaturization of solid-state imaging devices.

SUMMARY OF THE INVENTION

According to a first aspect of present invention, a solid-state imagingdevice includes a first substrate, a second substrate, and a connectionportion. The second substrate is laminated on the first substrate. Theconnection portion is disposed between the first substrate and thesecond substrate. The first substrate includes a plurality of pixels anda plurality of first control signal lines. The plurality of pixels arearranged in a matrix to output pixel signals according to controlsignals. The plurality of first control signal lines are connected topixels of each row in an array of the plurality of pixels. The secondsubstrate includes a plurality of second control signal lines and acontrol circuit. The plurality of second control signal lines arearranged in correspondence with the plurality of first control signallines. The control circuit is connected to the plurality of secondcontrol signal lines to output the control signals. An arrangement ofeach of the plurality of second control signal lines on the secondsubstrate corresponds to an arrangement of a corresponding one of theplurality of first control signal lines on the first substrate. Theconnection portion includes a plurality of control connections and aplurality of readout connections. Each of the plurality of controlconnections is connected to one of the plurality of first control signallines and a corresponding one of the plurality of second control signallines. The plurality of readout connections are configured to output thepixel signals output from the plurality of pixels to the secondsubstrate.

According to a second aspect of the present invention, in the firstaspect, the first substrate may further include a plurality of firstreadout signal lines, each being connected to pixels of each column inthe array of the plurality of pixels. Each of the plurality of readoutconnections may be connected to one of the plurality of first readoutsignal lines.

According to a third aspect of the present invention, in the secondaspect, the second substrate may further include a plurality of secondreadout signal lines arranged in correspondence with the plurality offirst readout signal lines. Each of the plurality of readout connectionsmay be connected to one of the plurality of first readout signal linesand a corresponding one of the plurality of second readout signal lines.

According to a fourth aspect of the present invention, in the firstaspect, the number of control connections connected to one of the firstcontrol signal lines connected to pixels in the same row in the array ofthe plurality of pixels may be smaller than the number of columns in thearray of the plurality of pixels.

According to a fifth aspect of the present invention, in the firstaspect, the number of readout connections to which the pixel signalsoutput from pixels of the same column in the array of the plurality ofpixels are input may be smaller than the number of rows in the array ofthe plurality of pixels.

According to a sixth aspect of the present invention, in the firstaspect, two or more of the control connections may be connected to oneof the plurality of first control signal lines and a corresponding oneof the plurality of second control signal lines.

According to a seventh aspect of the present invention, in the firstaspect, a cross-sectional area of each of the plurality of readoutconnections may be greater than a cross-sectional area of each of theplurality of control connections.

According to an eighth aspect of the present invention, in the firstaspect, the control circuit may be configured to output a plurality ofthe control signals that are provided to each of the plurality ofpixels. A length of a path of each of the plurality of the controlsignals from the control circuit to each of the plurality of pixels maybe different for each of the plurality of the control signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of an imaging deviceaccording to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a solid-stateimaging device according to the first embodiment of the presentinvention.

FIG. 3 is a cross-sectional view of the solid-state imaging deviceaccording to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of the solid-state imaging deviceaccording to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a first substrateincluded in the solid-state imaging device according to the firstembodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a second substrateincluded in the solid-state imaging device according to the firstembodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a shared pixelincluded in the solid-state imaging device according to the firstembodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a solid-stateimaging device according to a second embodiment of the presentinvention.

FIG. 9 is a cross-sectional view of the solid-state imaging deviceaccording to the second embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a first substrateincluded in the solid-state imaging device according to the secondembodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a second substrateincluded in the solid-state imaging device according to the secondembodiment of the present invention.

FIG. 12 is a cross-sectional view of a solid-state imaging deviceaccording to a third embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a first substrateincluded in the solid-state imaging device according to the thirdembodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a second substrateincluded in the solid-state imaging device according to the thirdembodiment of the present invention.

FIG. 15 is a cross-sectional view of a solid-state imaging deviceaccording to a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described withreference to the drawings.

First Embodiment

FIG. 1 shows a configuration of an imaging device 7 according to a firstembodiment of the present invention. The imaging device 7 may be anelectronic device having an imaging function. For example, the imagingdevice 7 is one of a digital camera, a digital video camera, anendoscope, and a microscope. As shown in FIG. 1, the imaging device 7includes a solid-state imaging device 1, a lens unit 2, an image signalprocessing device 3, a recording device 4, a camera control device 5,and a display device 6.

The solid-state imaging device 1 converts a subject image formed on alight receiving surface into a signal such as a captured image signaland outputs the signal. The lens unit 2 has a zoom lens and a focuslens. The lens unit 2 forms a subject image based on light from asubject on the light receiving surface of the solid-state imaging device1. Light received through the lens unit 2 is imaged on the lightreceiving surface of the solid-state imaging device 1.

The image signal processing device 3 performs predetermined processingon the signal output from the solid-state imaging device 1. Processingperformed by the image signal processing device 3 includes conversioninto image data, various correction of image data, compression of imagedata, or the like.

The recording device 4 has a semiconductor memory or the like forrecording or reading image data. The recording device 4 is attachable toand detachable from the imaging device 7. The display device 6 displaysan image based on image data processed by the image signal processingdevice 3 or image data read from the recording device 4.

The camera control device 5 controls the entirety of the imaging device7. Operations of the camera control device 5 are defined in a programstored in a ROM provided in the imaging device 7. The camera controldevice 5 reads this program and performs various sorts of controlaccording to content defined by the program.

FIG. 2 shows a configuration of the solid-state imaging device 1. Asshown in FIG. 2, the solid-state imaging device 1 includes a verticalreadout circuit 10 (a control circuit), a horizontal readout circuit 20,a pixel portion 30, a memory unit 31, a signal processing circuit 50,and an output unit 70.

The pixel portion 30 has a plurality of pixels 40. Although a pluralityof pixels 40 are arranged in FIG. 2, a reference numeral of a singlepixel 40 is shown as a representative. The plurality of pixels 40 arearranged in a matrix. The plurality of pixels 40 output pixel signalsaccording to control signals. The plurality of pixels 40 are connectedto the memory unit 31. The plurality of pixels 40 output pixel signalsto the memory unit 31. The memory unit 31 holds the pixel signals outputfrom the plurality of pixels 40. The pixel signals held in the memoryunit 31 are output to the signal processing circuit 50.

The vertical readout circuit 10 controls reading of pixel signals fromthe plurality of pixels 40. More specifically, the vertical readoutcircuit 10 outputs control signals for controlling reading of pixelsignals to control signal lines 80. The control signals are transferredto the plurality of pixels 40 through the control signal lines 80.Through these control signals, pixel signals are simultaneously readfrom two or more pixels 40 arranged in the same row in the array of theplurality of pixels 40.

The signal processing circuit 50 performs signal processing on pixelsignals under the control of the horizontal readout circuit 20. Forexample, the signal processing circuit 50 performs processing such asnoise suppression by correlated double sampling (CDS).

The horizontal readout circuit 20 reads out the pixel signals processedby the signal processing circuit 50 to a horizontal signal line 60. Morespecifically, the horizontal readout circuit 20 outputs, to the signalprocessing circuit 50, control signals for controlling signal processingof the signal processing circuit 50 and reading of pixel signals. Bythis control, pixel signals output from two or more pixels 40 arrangedin the same row in the array of the plurality of pixels 40 aresequentially read out to the horizontal signal line 60.

The output unit 70 outputs pixel signals processed by the signalprocessing circuit 50 to the outside. More specifically, the output unit70 appropriately performs processing such as amplification processing onthe pixel signals processed by the signal processing circuit 50. Theoutput unit 70 then outputs the processed pixel signals to the outside.

FIGS. 3 and 4 show different cross sections of the solid-state imagingdevice 1. As shown in FIGS. 3 and 4, the solid-state imaging device 1includes a first substrate 100, a second substrate 110, and a connectionportion 120. The second substrate 110 is laminated on the firstsubstrate 100. The connection portion 120 is disposed between the firstsubstrate 100 and the second substrate 110.

The connection portion 120 has a plurality of control connections 13 anda plurality of readout connections 14. A single control connection 13 isshown in FIG. 3. The plurality of control connections 13 and theplurality of readout connections 1.4 electrically connect the firstsubstrate 100 and the second substrate 110. The plurality of controlconnections 13 transfer control signals between the first substrate 100and the second substrate 110. The plurality of readout connections 14transfer pixel signals between the first substrate 100 and the secondsubstrate 110.

The first substrate 100 further includes a plurality of first controlsignal lines 80A. A single first control signal line 80A is shown inFIG. 3. The second substrate 110 further includes a plurality of secondcontrol signal lines 80B. A single second control signal line 80B isshown in FIG. 3. The plurality of first control signal lines 80A and theplurality of second control signal lines 80B correspond to the controlsignal lines 80 in FIG. 2. The plurality of first control signal lines80A transfer control signals on the first substrate 100. The pluralityof second control signal lines 80B transfer control signals on thesecond substrate 110.

FIG. 5 shows a configuration of the first substrate 100. As shown inFIG. 5, the first substrate 100 includes the pixel portion 30 and theplurality of first control signal lines 80A. The positions of theplurality of control connections 13 and the plurality of readoutconnections 14 are shown in FIG. 5. The sizes of the plurality ofcontrol connections 13 and the plurality of readout connections 14 arenot shown in FIG. 5. Although a plurality of control connections 13 arearranged in FIG. 5, a reference numeral of a single control connection13 is shown as a representative. Although a plurality of readoutconnections 14 are arranged in FIG. 5, a reference numeral of a singlereadout connection 14 is shown as a representative. Although a pluralityof first control signal lines 80A are arranged in FIG. 5, a referencenumeral of four first control signal lines 80A is shown as arepresentative.

The pixel portion 30 has a plurality of pixels 40. Although a pluralityof pixels 40 are arranged in FIG. 5, a reference numeral of a singlepixel 40 is shown as a representative. The plurality of pixels 40 arearranged in a matrix. The plurality of pixels 40 output pixel signalsaccording to control signals. The pixel portion 30 includes a pluralityof shared pixels 35. Although a plurality of shared pixels 35 arearranged in FIG. 5, a reference numeral of a single shared pixel 35 isshown as a representative. Each of the plurality of shared pixels 35includes two or more pixels 40. In FIG. 5, each of the plurality ofshared pixels 35 includes two pixels 40 arranged in a column directionof the array of the plurality of pixels 40. Two pixels 40 included inone shared pixel 35 share a part of a circuit constituting the pixels40.

The plurality of first control signal lines 80A are arranged in a rowdirection of the array of the plurality of pixels 40. The plurality offirst control signal lines 80A are connected to pixels 40 of each row inthe array of the plurality of pixels 40. Each of the plurality ofcontrol connections 13 is connected to one of the plurality of firstcontrol signal lines 80A. In FIG. 5, a single control connection 13 isconnected to a single first control signal line 80A. Control signalstransferred to the first substrate 100 through the plurality of controlconnections 13 are transferred to the plurality of pixels 40 through theplurality of first control signal lines 80A.

Four control signals are shown in FIG. 5. The four control signals are acontrol signal φTX1, a control signal φTX2, a control signal φRST, and acontrol signal φSEL. These control signals will be described later. Atleast a part of the plurality of first control signal lines 80A iscommonly connected to two pixels 40 included in one shared pixel 35.Therefore, at least a part of the plurality of control signals iscommonly provided to two pixels 40 included in one shared pixel 35.

The number of control connections 13 connected to one first controlsignal line 80A connected to pixels 40 in the same row in the array ofthe plurality of pixels 40 may be smaller than the number of columns inthe array of the plurality of pixels 40. In FIG. 5, the number ofcontrol connections 13 connected to one first control signal line 80Aconnected to pixels 40 in the same row is 1. In FIG. 5, the number ofcolumns in the array of the plurality of pixels 40 is 4.

The plurality of pixels 40 output pixel signals according to controlsignals. Each of the plurality of pixels 40 is connected to one of theplurality of readout connections 14. That is, each of the plurality ofreadout connections 14 is arranged so as to correspond to each of twopixels 40 included in a corresponding shared pixel 35. The plurality ofreadout connections 14 output the pixel signals output from theplurality of pixels 40 to the second substrate 110. That is, the pixelsignals output from the plurality of pixels 40 are transferred to thesecond substrate 110 through the plurality of readout connections 14.

FIG. 6 shows a configuration of the second substrate 110. As shown inFIG. 6, the second substrate 110 includes a vertical readout circuit 10,a horizontal readout circuit 20, a memory unit 31, a signal processingcircuit 50, an output unit 70, and a plurality of second control signallines 80B. The positions of the plurality of control connections 13 andthe plurality of readout connections 14 are shown in FIG. 6. The sizesof the plurality of control connections 13 and the plurality of readoutconnections 14 are not shown in FIG. 6. Although a plurality of controlconnections 13 are arranged in FIG. 6, a reference numeral of a singlecontrol connection 13 is shown as a representative. Although a pluralityof readout connections 14 are arranged in FIG. 6, a reference numeral ofa single readout connection 14 is shown as a representative. Although aplurality of second control signal lines 80B are arranged in FIG. 6, areference numeral of four second control signal lines 80B is shown as arepresentative.

The plurality of second control signal lines 80B are arranged in the rowdirection of the array of the plurality of pixels 40. The plurality ofsecond control signal lines 80B are arranged in correspondence with theplurality of first control signal lines 80A. Each of the plurality ofcontrol connections 13 is connected to one of the plurality of secondcontrol signal lines 80B. In FIG. 6, a single control connection 13 isconnected to a single second control signal line 80B. As shown in FIGS.5 and 6, each of the plurality of control connections 13 is connected toone of the plurality of first control signal lines 80A and acorresponding one of the plurality of second control signal lines 80B.Positions in the row direction of the plurality of control connections13 corresponding to different control signals are different from eachother. For example, a position in the row direction of a controlconnection 13 corresponding to the control signal φTX1 is different froma position in the row direction of a control connection 13 correspondingto the control signal ∠TX2. Two or more control connections 13 may beconnected to one of the plurality of first control signal lines 80A anda corresponding one of the plurality of second control signal lines 80B.

The vertical readout circuit 10 is connected to a plurality of secondcontrol signal lines 80B. The vertical readout circuit 10 outputscontrol signals. The control signals output from the vertical readoutcircuit 10 are transferred to the plurality of control connections 13through the plurality of second control signal lines 80B. The pluralityof control connections 13 output the control signals output from thevertical readout circuit 10 to the first substrate 100.

The plurality of readout connections 14 output pixel signals output fromthe plurality of pixels 40 to the second substrate 110. The plurality ofreadout connections 14 are connected to the memory unit 31. The pixelsignals transferred through the plurality of readout connections 14 areinput to the memory unit 31. The horizontal readout circuit 20, thememory unit 31, the signal processing circuit 50, and the output unit 70have already been described and therefore descriptions thereof areomitted.

The vertical readout circuit 10 outputs a plurality of control signalsprovided to each of the plurality of pixels 40. Four control signals areshown in FIG. 6. The four control signals are the control signal φTX1,the control signal φTX2, the control signal φRST, and the control signalφSEL. Each of the control signal φTX1 and the control signal φTX2corresponds to one of the two pixels 40 constituting a shared pixel 35.The control signal φRST and the control signal φSEL commonly correspondto the two pixels 40 constituting the shared pixel 35.

The length of a path of each of the plurality of control signals fromthe vertical readout circuit 10 to each of the plurality of pixels 40 isdifferent for each of the plurality of control signals. The length ofthe path of each of the plurality of control signals is the sum of thelength of the second control signal line 80B from the vertical readoutcircuit 10 to the control connection 13 and the length of the firstcontrol signal line 80A from the control connection 13 to the pixel 40.For example, the length of the path of the control signal φTX1 isdifferent from the length of the path of the control signal φTX2.

The control connection 13 can be disposed at an arbitrary positionbetween the first control signal line 80A and the second control signalline 80B. Therefore, as shown in FIGS. 5 and 6, it is possible todispose a plurality of control connections 13 such that positions in therow direction of a plurality of control connections 13 corresponding toa plurality of different control signals are different from each other.This enlarges a region in which the plurality of control connections 13can be arranged.

FIG. 7 shows a configuration of a shared pixel 35. As shown in FIG. 7,the shared pixel 35 includes a plurality of pixel circuits 40 a anamplification transistor Ma, a reset transistor Mrst, and a selectiontransistor Msel. Each of the plurality of pixels 40 has a pixel circuit40 a. The plurality of pixels 40 share the amplification transistor Ma,the reset transistor Mrst, and the selection transistor Msel. In FIG. 7,the plurality of pixel circuits 40 a constituting the shared pixel 35are arranged in a lateral direction of FIG. 7 to avoid complicating thearrangement of each element.

The pixel circuit 40 a includes a photoelectric conversion element PDkand a transfer transistor Mtxk. k is an integer from 1 to n. n is aninteger of 2 or more. n is the number of pixels 40 constituting theshared pixel 35. The transfer transistor Mtxk, the amplificationtransistor Ma, the reset transistor Mrst, and the selection transistorMsel are N-type transistors. These transistors may also be P-typetransistors.

An input terminal of the photoelectric conversion element PDk isconnected to ground. A drain of the transfer transistor Mtxk isconnected to an output terminal of the photoelectric conversion elementPDk. A gate of the transfer transistor Mtxk is connected to a firstcontrol signal line 80A. The control signal φTXk is input to the gate ofthe transfer transistor Mtxk.

A source of the reset transistor Mrst is connected to a power supplyterminal. A power supply voltage VDD is input to the power supplyterminal. A drain of the reset transistor Mrst is connected to thesources of the plurality of transfer transistors Mtxk. A gate of thereset transistor Mrst is connected to a first control signal line 80A.The control signal φRST is provided to the reset transistor Mrst.

A drain of the amplification transistor Ma is connected to the powersupply terminal. A gate of the amplification transistor Ma is connectedto the sources of the plurality of transfer transistors Mtxk. A drain ofthe selection transistor Msel is connected to a source of theamplification transistor Ma. A source of the selection transistor Mselis connected to a readout connection 14. A gate of the selectiontransistor Msel is connected to a first control signal line 80A. Thecontrol signal φSEL is provided to the selection transistor Msel.

For example, the photoelectric conversion element PDk is a photodiode.The photoelectric conversion element PDk generates electric charge basedon the amount of light incident on the solid-state imaging device 1. Thephotoelectric conversion element PDk holds the generated electriccharge. The transfer transistor Mtxk transfers the electric charge heldat the photoelectric conversion element PDk to the gate of theamplification transistor Ma. On/off of the transfer transistor Mtxk iscontrolled by the control signal φTXk. Electric charge transferred bythe transfer transistor Mtxk is held at the gate of the amplificationtransistor Ma.

The reset transistor Mist resets electric charge held at thephotoelectric conversion element PDk and electric charge held at thegate of the amplification transistor Ma. On/off of the reset transistorMrst is controlled by the control signal φMT. Electric charge held atthe photoelectric conversion element PDk is reset by simultaneouslyturning on the reset transistor Mist and the transfer transistor Mtxk.

The amplification transistor Ma outputs a pixel signal obtained byamplifying a signal based on electric charge held at the gate throughthe source. The selection transistor Msel reads the pixel signal outputfrom the amplification transistor Ma and outputs the pixel signal to thereadout connection 14. On/off of the selection transistor Msel iscontrolled by the control signal φSEL.

The control signal φRST and the control signal φSEL are commonlyprovided to two or more pixels 40 included in one shared pixel 35.Therefore, a first control signal line 80A transferring the controlsignal φRST and a first control signal line 80A transferring the controlsignal φSEL are commonly connected to two or more pixels 40 included inone shared pixel 35.

A part of the circuit constituting the plurality of pixels 40 need notbe shared by two or more pixels 40. That is, each of the plurality ofpixels 40 may be independent of the other pixels 40. The configurationof the pixel 40 is not limited to the configuration shown in FIG. 7.

The solid state imaging device according to each aspect of the presentinvention need not have a configuration corresponding to at least one ofthe horizontal readout circuit 20, the memory unit 31, the signalprocessing circuit 50, and the output unit 70.

According to the first embodiment, the solid-state imaging device 1 isconfigured to include the first substrate 100, the second substrate 110,and the connection portion 120. The first substrate 100 has a pluralityof pixels 40 and a plurality of first control signal lines 80A. Thesecond substrate 110 has a plurality of second control signal lines 80Band a vertical readout circuit 10 (a control circuit). The connectionportion 120 has a plurality of control connections 13 and a plurality ofreadout connections 14.

In the first embodiment, the plurality of first control signal lines 80Aare arranged on the first substrate 100 and the plurality of secondcontrol signal lines 80B are arranged on the second substrate 110. Eachof the plurality of control connections 13 is connected to one of theplurality of first control signal lines 80A and a corresponding one ofthe plurality of second control signal lines 80B. This enlarges a regionin which the plurality of control connections 13 can be arranged. As aresult, the pitch of control connections 13 is increased and thereforeit is possible to reduce defects in electrical connection between thetwo substrates. Thus, the yield is improved.

The number of control connections 13 connected to one first controlsignal line 80A connected to pixels 40 in the same row in the array ofthe plurality of pixels 40 may be smaller than the number of columns inthe array of the plurality of pixels 40. This increases the pitch ofcontrol connections 13. As a result, contact between two controlconnections 13 is avoided. That is, it is possible to reduce defects inelectrical connection between the two substrates.

Two or more control connections 13 may be connected to one of theplurality of first control signal lines 80A and a corresponding one ofthe plurality of second control signal lines 80B. The resistance of acontrol signal path between the first substrate 100 and the secondsubstrate 110 is reduced by connecting two or more control connections13 to one first control signal line 80A and one second control signalline 80B. This reduces voltage drop of the control signals. The pixels40 may not operate properly due to voltage drop of the control signals.Reducing the voltage drop of the control signals reduces defectiveoperations of the pixels 40.

Second Embodiment

In a second embodiment of the present invention, the solid-state imagingdevice 1 shown in FIG. 2 is replaced with a solid-state imaging device1A shown in FIG. 8. FIG. 8 shows a configuration of the solid-stateimaging device 1A. As shown in FIG. 8, the solid-state imaging device 1Aincludes a vertical readout circuit 10 (a control circuit), a horizontalreadout circuit 20, a pixel portion 30, a signal processing circuit 50,and an output unit 70.

Parts of the configuration shown in FIG. 8 different from theconfiguration shown in FIG. 2 are described below.

In the solid-state imaging device 1A, the memory unit 31 in thesolid-state imaging device 1 shown in FIG. 2 has been removed. Pixelsignals output from a plurality of pixels 40 are transferred to thesignal processing circuit 50 through vertical signal lines 90.

Parts other than the above of the configuration shown in FIG. 8 are thesame as those of the configuration shown in FIG. 2.

FIG. 9 shows a cross-section of the solid-state imaging device 1A. Asshown in FIG. 9, the solid-state imaging device 1A includes a firstsubstrate 101, a second substrate 111, and a connection portion 120.

Parts of the configuration shown in FIG. 9 different from theconfiguration shown in FIG. 4 are described below.

In the solid-state imaging device 1A, the first substrate 100 shown inFIG. 4 is replaced with the first substrate 101 shown in FIG. 9. In thesolid-state imaging device 1A, the second substrate 110 shown in FIG. 4is also replaced with the second substrate 111 shown in FIG. 9.

The first substrate 101 has a plurality of first vertical signal lines90A (first readout signal lines). Although a plurality of first verticalsignal lines 90A are provided in FIG. 9, a reference numeral of a singlefirst vertical signal line 90A is shown as a representative. Theplurality of first vertical signal lines 90A correspond to the verticalsignal lines 90 in FIG. 8. The plurality of first vertical signal lines90A transfer pixel signals on the first substrate 101.

Parts other than the above of the configuration shown in FIG. 9 are thesame as those of the configuration shown in FIG. 4. A cross-sectionincluding a control connection 13 of the solid-state imaging device 1Ais the same as the cross-section of the solid-state imaging device 1shown in FIG. 3.

FIG. 10 shows a configuration of the first substrate 101. As shown inFIG. 10, the first substrate 101 includes a pixel portion 30, aplurality of first control signal lines 80A, and a plurality of firstvertical signal lines 90A. The positions of a plurality of controlconnections 13 and a plurality of readout connections 14 are shown inFIG. 10. The sizes of the plurality of control connections 13 and theplurality of readout connections 14 are not shown in FIG. 10. Although aplurality of control connections 13 are arranged in FIG. 10, a referencenumeral of a single control connection 13 is shown as a representative.Although a plurality of readout connections 14 are arranged in FIG. 10,a reference numeral of a single readout connection 14 is shown as arepresentative. Although a plurality of first control signal lines 80Aare arranged in FIG. 10, a reference numeral of four first controlsignal lines 80A is shown as a representative. Although a plurality offirst vertical signal lines 90A are arranged in FIG. 10, a referencenumeral of a single first vertical signal line 90A is shown as arepresentative.

Parts of the configuration shown in FIG. 10 different from theconfiguration shown in FIG. 5 are described below.

The plurality of first vertical signal lines 90A are arranged in acolumn direction of the array of the plurality of pixels 40. Each of theplurality of first vertical signal lines 90A is connected to pixels 40of each column in the array of the plurality of pixels 40. Each of theplurality of readout connections 14 is connected to one of the pluralityof first vertical signal lines 90A. In FIG. 10, a single readoutconnection 14 is connected to a single first vertical signal line 90A.Pixel signals output from the plurality of pixels 40 are transferred tothe plurality of readout connections 14 through the plurality of firstvertical signal lines 90A. The plurality of readout connections 14output the pixel signals output from the plurality of pixels 40 to thesecond substrate 111.

At least a part of the plurality of first vertical signal lines 90A iscommonly connected to two pixels 40 included in one shared pixel 35.Therefore, pixel signals are output from two pixels 40 included in oneshared pixel 35 to the common first vertical signal line 90A.

The first vertical signal lines 90A are arranged on the first substrate101. Pixel signals output from pixels 40 in the same column in the arrayof the plurality of pixels 40 are transferred to one readout connection14 through one first vertical signal line 90A. Therefore, the number ofreadout connections 14 to which pixel signals output from pixels 40 inthe same column in the array of the plurality of pixels 40 are input canbe reduced compared to the first substrate 100 shown in FIG. 5. In thefirst substrate 100 shown in FIG. 5, the number of readout connections14 to which pixel signals output from pixels 40 in the same column areinput is 2. In the first substrate 101 shown in FIG. 10, the number ofreadout connections 14 to which pixel signals output from pixels 40 inthe same column are input is 1. This enlarges a region in which theplurality of control connections 13 can be arranged.

The number of readout connections 14 to which pixel signals output frompixels 40 in the same column in the array of the plurality of pixels 40are input may be smaller than the number of rows in the array of theplurality of pixels 40. In FIG. 10, the number of readout connections 14connected to one first vertical signal line 90A connected to pixels 40in the same column is 1. In FIG. 10, the number of rows in the array ofthe plurality of pixels 40 is 4.

In FIG. 5, the plurality of readout connections 14 are arranged in aregion in which the plurality of pixels 40 are arranged, that is, insidea pixel region. In FIG. 10, the plurality of readout connections 14 arearranged outside the pixel region. The plurality of readout connections14 may also be arranged inside the pixel region. In FIG. 10, the regionin which the plurality of control connections 13 can be arranged isenlarged compared to the case where the plurality of readout connections14 are arranged inside the pixel region.

Parts other than the above of the configuration shown in FIG. 10 are thesame as those of the configuration shown in FIG. 5.

FIG. 11 shows a configuration of the second substrate 111. As shown inFIG. 11, the second substrate 111 includes a vertical readout circuit10, a horizontal readout circuit 20, a signal processing circuit 50, anoutput unit 70, and a plurality of second control signal lines 80B. Thepositions of the plurality of control connections 13 and the pluralityof readout connections 14 are shown in FIG. 11. The sizes of theplurality of control connections 13 and the plurality of readoutconnections 14 are not shown in FIG. 11. Although a plurality of controlconnections 13 are arranged in FIG. 11, a reference numeral of a singlecontrol connection 13 is shown as a representative. Although a pluralityof readout connections 14 are arranged in FIG. 11, a reference numeralof a single readout connection 14 is shown as a representative. Althougha plurality of second control signal lines 80B are arranged in FIG. 11,a reference numeral of four second control signal lines 80B is shown asa representative.

Parts of the configuration shown in FIG. 11 different from configurationshown in FIG. 6 are described below.

In the second substrate 111, the memory unit 31 in the second substrate110 shown in FIG. 6 has been removed. The plurality of readoutconnections 14 are connected to the signal processing circuit 50. Theplurality of readout connections 14 constitute an input portion of thesignal processing circuit 50. Pixel signals transferred through theplurality of readout connections 14 are input to the signal processingcircuit 50. Since the signal processing circuit 50 has already beendescribed, a description of the signal processing circuit 50 is omitted.

Parts other than the above of the configuration shown in FIG. 11 are thesame as those of the configuration shown in FIG. 6.

According to the second embodiment, the solid-state imaging device 1A isconfigured to include the first substrate 101, the second substrate 111,and the connection portion 120. The first substrate 101 has a pluralityof pixels 40, a plurality of first control signal lines 80A, and aplurality of first vertical signal lines 90A (first readout signallines). The second substrate 111 has a plurality of second controlsignal lines 80B and a vertical readout circuit 10 (control circuit).The connection portion 120 has a plurality of control connections 13 anda plurality of readout connections 14.

In the second embodiment, a plurality of first control signal lines 80Aare arranged on the first substrate 101 and a plurality of secondcontrol signal lines 80B are arranged on the second substrate 111. Eachof the plurality of control connections 13 is connected to one of theplurality of first control signal lines 80A and a corresponding one ofthe plurality of second control signal lines 80B. This enlarges a regionin which the plurality of control connections 13 can be arranged. As aresult, the pitch of control connections 13 is increased and thereforeit is possible to reduce defects in electrical connection between thetwo substrates. Thus, the yield is improved.

In the second embodiment, each of the plurality of readout connections14 is connected to one of the plurality of first vertical signal lines90A. This can reduce the number of readout connections 14 to which pixelsignals output from pixels 40 in the same column in the array of theplurality of pixels 40 are input. As a result, a region in which theplurality of control connections 13 can be arranged is enlarged. Thatis, defects in electrical connection between the two substrates can bereduced.

The number of readout connections 14 to which pixel signals output frompixels 40 in the same column in the array of the plurality of pixels 40are input may be smaller than the number of rows in the array of theplurality of pixels 40. This increases the pitch of readout connections14. As a result, contact between two readout connections 14 is avoided.That is, defects in electrical connection between the two substrates canbe reduced.

Third Embodiment

In a third embodiment of the present invention, the solid-state imagingdevice 1A shown in FIG. 9 is replaced with a solid-state imaging device1B shown in FIG. 12. FIG. 12 shows a cross-section of the solid-stateimaging device 1B. As shown in FIG. 12, the solid-state imaging device13 includes a first substrate 102, a second substrate 112, and aconnection portion 120.

Parts of the configuration shown in FIG. 12 different from theconfiguration shown in FIG. 9 are described below.

In the solid-state imaging device 1B, the first substrate 101 shown inFIG. 9 is replaced with the first substrate 102 shown in FIG. 12. In thesolid-state imaging device 1b, the second substrate 111 shown in FIG. 9is also replaced with the second substrate 112 shown in FIG. 12.

Positions at which the plurality of readout connections 14 are arrangedon the first substrate 102 are different from positions at which theplurality of readout connections 14 are arranged on the first substrate101 shown in FIG. 9. The second substrate 112 has a plurality of secondvertical signal lines 90B (second readout signal lines). Although aplurality of second vertical signal lines 90B are provided in FIG. 12, areference numeral of a single second vertical signal line 90B is shownas a representative. The plurality of first vertical signal lines 90Aand the plurality of second vertical signal lines 90B correspond to thevertical signal lines 90 in FIG. 8. The plurality of second verticalsignal lines 90B transfer pixel signals on the second substrate 112.

Parts other than the above of the configuration shown in FIG. 12 are thesame as those of the configuration shown in FIG. 9. A cross-sectionincluding a control connection 13 of the solid-state imaging device 1Bis the same as the cross-section of the solid-state imaging device 1shown in FIG. 3.

FIG. 13 shows a configuration of the first substrate 102. As shown inFIG. 13, the first substrate 102 has a pixel portion 30, a plurality offirst control signal lines 80A, and a plurality of first vertical signallines 90A (first readout signal lines). The positions of the pluralityof control connections 13 and the plurality of readout connections 14are shown in FIG. 13. The sizes of the plurality of control connections13 and the plurality of readout connections 14 are not shown in FIG. 13.Although a plurality of control connections 13 are arranged in FIG. 13,a reference numeral of a single control connection 13 is shown as arepresentative. Although a plurality of readout connections 14 arearranged in FIG. 13, a reference numeral of a single readout connection14 is shown as a representative. Although a plurality of first controlsignal lines 80A are arranged in FIG. 13, a reference numeral of tourfirst control signal lines 80A is shown as a representative. Although aplurality of first vertical signal lines 90A are arranged in FIG. 13, areference numeral of a single first vertical signal line 90A is shown asa representative.

Parts of the configuration shown in FIG. 13 different from theconfiguration shown in FIG. 10 are described below

The plurality of readout connections 14 are arranged in a region inwhich the plurality of pixels 40 are arranged, that is, inside a pixelregion. Positions in the column direction of two readout connections 14corresponding to two adjacent columns in the array of the plurality ofpixels 40 are different from each other.

Parts other than the above of the configuration shown in FIG. 13 are thesame as those of the configuration shown in FIG. 10.

FIG. 14 shows a configuration of the second substrate 112. As shown inFIG. 14, the second substrate 112 includes a vertical readout circuit10, a horizontal readout circuit 20, a signal processing circuit 50, anoutput unit 70, a plurality of second control signal lines 80B, and aplurality of second vertical signal lines 90B. The positions of theplurality of control connections 13 and the plurality of readoutconnections 14 are shown in FIG. 14. The sizes of the plurality ofcontrol connections 13 and the plurality of readout connections 14 arenot shown in FIG. 14. Although a plurality of control connections 13 arearranged in FIG. 14, a reference numeral of a single control connection13 is shown as a representative. Although a plurality of readoutconnections 14 are arranged in FIG. 14, a reference numeral of a singlereadout connection 14 is shown as a representative. Although a pluralityof second control signal lines 80B are arranged in FIG. 14, a referencenumeral of four second control signal lines 80B are shown as arepresentative. Although a plurality of second vertical signal lines 90Bare arranged in FIG. 14, a reference numeral of a single second verticalsignal line 90B is shown as a representative.

Parts of the configuration shown in FIG. 14 different from theconfiguration shown in FIG. 11 are described below.

The plurality of second vertical signal lines 90B are arranged in thecolumn direction of the array of the plurality of pixels 40. Theplurality of second vertical signal lines 90B are arranged incorrespondence with the plurality of first vertical signal lines 90A.Each of the plurality of readout connections 14 is connected to one ofthe plurality of second vertical signal lines 90B. In FIG. 14, a singlereadout connection 14 is connected to a single second vertical signalline 90B. As shown in FIGS. 13 and 14, each of the plurality of readoutconnections 14 is connected to one of the plurality of first verticalsignal lines 90A and a corresponding one of the plurality of secondvertical signal lines 90B. Two or more readout connections 14 may beconnected to one of the plurality of first vertical signal lines 90A anda corresponding one of the plurality of second vertical signal lines90B.

The plurality of second vertical signal lines 90B are connected to aninput portion of the signal processing circuit 50. Pixel signalstransferred through the plurality of readout connections 14 aretransferred to the input portion of the signal processing circuit 50through the plurality of second vertical signal lines 90B. Since thesignal processing circuit 50 has already been described, a descriptionof the signal processing circuit 50 is omitted.

Parts other than the above of the configuration shown in FIG. 14 are thesame as those of the configuration shown in FIG. 11.

The readout connection 14 can be arranged at an arbitrary positionbetween the first vertical signal line 90A and the second verticalsignal line 90B. Therefore, as shown in FIGS. 13 and 14, it is possibleto dispose a plurality of readout connections 14 such that positions inthe column direction of two readout connections 14 corresponding to twoadjacent columns in the array of the plurality of pixels 40 aredifferent from each other. This enlarges a region in which the pluralityof readout connections 14 can be arranged.

According to the third embodiment, the solid-state imaging device 1B isconfigured to include the first substrate 102, the second substrate 112,and the connection portion 120. The first substrate 102 has a pluralityof pixels 40, a plurality of first control signal lines 80A, and aplurality of first vertical signal lines 90A (first readout signallines). The second substrate 112 has a plurality of second controlsignal lines 80B, a vertical readout circuit 10 (a control circuit), anda plurality of second vertical signal lines 90B (second readout signallines). The connection portion 120 has a plurality of controlconnections 13 and a plurality of readout connections 14.

In the third embodiment, a plurality of first control signal lines 80Aare arranged on the first substrate 102 and a plurality of secondcontrol signal lines 80B are arranged on the second substrate 112. Eachof the plurality of control connections 13 is connected to one of theplurality of first control signal lines 80A and a corresponding one ofthe plurality of second control signal lines 80B. This enlarges a regionin which the plurality of control connections 13 can be arranged. As aresult, the pitch of control connections 13 is increased and thereforeit is possible to reduce defects in electrical connection between thetwo substrates. Thus, the yield is improved.

In the third embodiment, each of the plurality of readout connections 14is connected to one of the plurality of first vertical signal lines 90Aand a corresponding one of the plurality of second vertical signal lines90B. This enlarges a region in which the plurality of readoutconnections 14 can be arranged. As a result, the pitch of readoutconnections 14 is increased and therefore it is possible to reducedefects in electrical connection between the two substrates.

Two or more readout connections 14 may be connected to one of theplurality of first vertical signal lines 90A and a corresponding one ofthe plurality of second vertical signal lines 90B. The resistance of apixel signal path between the first substrate 102 and the secondsubstrate 112 is reduced by connecting two or more readout connections14 to one first vertical signal line 90A and one second vertical signalline 90B. This reduces voltage drop of pixel signals. As a result,deterioration in image quality is reduced.

Fourth Embodiment

In a fourth embodiment of the present invention, the solid-state imagingdevice 1B shown in FIG. 12 is replaced with a solid-state imaging device1C shown in FIG. 15. FIG. 15 shows a cross-section of the solid-stateimaging device 1C. As shown in FIG. 15, the solid-state imaging device1C includes a first substrate 102, a second substrate 112, and aconnection portion 120.

Parts of the configuration shown in FIG. 1.5 different from theconfiguration shown in FIG. 12 are described below.

A readout connection 14 in the solid-state imaging device 10 isconfigured to be thicker than the readout connection 14 in thesolid-state imaging device 1B shown in FIG. 12. Therefore, thecross-sectional area of each of a plurality of readout connections 14 isgreater than the cross-sectional area of each of the plurality ofcontrol connections 13. The cross-sectional area of a readout connection14 is a cross-sectional area of the readout connection 14 in a planeperpendicular to the lamination direction of the first substrate 102 andthe second substrate 112. Similarly, the cross-sectional area of acontrol connection 13 is a cross-sectional area of the controlconnection 13 in a plane perpendicular to the lamination direction ofthe first substrate 102 and the second substrate 112.

Parts other than the above of the configuration shown in FIG. 15 are thesame as those of the configuration shown in FIG. 12. A cross-sectionincluding a control connection 13 of the solid-state imaging device 1Cis the same as the cross-section of the solid-state imaging device 1shown in FIG. 3.

In the solid-state imaging device 1 shown in FIGS. 3 and 4, thecross-sectional area of each of the plurality of readout connections 14may be greater than the cross-sectional area of each of the plurality ofcontrol connections 13. In the solid-state imaging device 1A shown inFIG. 9, the cross-sectional area of each of the plurality of readoutconnections 14 may be greater than the cross-sectional area of each ofthe plurality of control connections 13. In the solid-state imagingdevice 113 shown in FIG. 12, the cross-sectional area of each of theplurality of readout connections 14 may be greater than thecross-sectional area of each of the plurality of control connections 13.

According to the fourth embodiment, the solid-state imaging device 1C isconfigured to include the first substrate 102, the second substrate 112,and the connection portion 120. The first substrate 102 has a pluralityof pixels 40, a plurality of first control signal lines 80A, and aplurality of first vertical signal lines 90A (first readout signallines). The second substrate 112 has a plurality of second controlsignal lines 80B, a vertical readout circuit 10 (a control circuit), anda plurality of second vertical signal lines 90B (second readout signallines). The connection portion 120 has a plurality of controlconnections 13 and a plurality of readout connections 14.

In the fourth embodiment, a plurality of first control signal lines 80Aare arranged on the first substrate 102 and a plurality of secondcontrol signal lines 80B are arranged on the second substrate 112. Eachof the plurality of control connections 13 is connected to one of theplurality of first control signal lines 80A and a corresponding one ofthe plurality of second control signal lines 80B. This enlarges a regionin which the plurality of control connections 13 can be arranged. As aresult, the pitch of control connections 13 is increased and thereforeit is possible to reduce detects in electrical connection between thetwo substrates. Thus, the yield is improved.

In the fourth embodiment, the cross-sectional area of each of theplurality of readout connections 14 is greater than the cross-sectionalarea of each of the plurality of control connections 13. This reducesthe resistances of the plurality of readout connections 14. As a result,the voltage drop of pixel signals is reduced.

While preferred embodiments of the invention have been described andshown above, it should be understood that these are exemplary of theinvention and are not to be considered as limiting. Additions,omissions, substitutions, and other modifications can be made withoutdeparting from the spirit or scope of the present invention.Accordingly, the invention is not to be considered as being limited bythe foregoing description, and is only limited by the scope of theappended claims.

What is claimed is:
 1. A solid-state imaging device, comprising: a firstsubstrate; a second substrate laminated on the first substrate; and aconnection portion disposed between the first substrate and the secondsubstrate; wherein the first substrate includes: a plurality of pixelsarranged in a matrix to output pixel signals according to controlsignals; and a plurality of first control signal lines connected topixels of each row in an array of the plurality of pixels, wherein thesecond substrate includes: a plurality of second control signal linesarranged in correspondence with the plurality of first control signallines; and a control circuit connected to the plurality of secondcontrol signal lines to output the control signals, wherein anarrangement of each of the plurality of second control signal lines onthe second substrate corresponds to an arrangement of a correspondingone of the plurality of first control signal lines on the firstsubstrate, and wherein the connection portion includes: a plurality ofcontrol connections, each being connected to one of the plurality offirst control signal lines and a corresponding one of the plurality ofsecond control signal lines; and a plurality of readout connectionsconfigured to output the pixel signals output from the plurality ofpixels to the second substrate.
 2. The solid-state imaging deviceaccording to claim 1, wherein the first substrate further includes aplurality of first readout signal lines, each being connected to pixelsof each column in the array of the plurality of pixels, and each of theplurality of readout connections is connected to one of the plurality offirst readout signal lines.
 3. The solid-state imaging device accordingto claim 2, wherein the second substrate further includes a plurality ofsecond readout signal lines arranged in correspondence with theplurality of first readout signal lines, and each of the plurality ofreadout connections is connected to one of the plurality of firstreadout signal lines and a corresponding one of the plurality of secondreadout signal lines.
 4. The solid-state imaging device according toclaim 1, wherein the number of control connections connected to one ofthe first control signal lines connected to pixels in the same row inthe array of the plurality of pixels is smaller than the number ofcolumns in the array of the plurality of pixels.
 5. The solid-stateimaging device according to claim 1, wherein the number of readoutconnections to which the pixel signals output from pixels of the samecolumn in the array of the plurality of pixels are input is smaller thanthe number of rows in the array of the plurality of pixels.
 6. Thesolid-state imaging device according to claim 1, wherein two or more ofthe control connections are connected to one of the plurality of firstcontrol signal lines and a corresponding one of the plurality of secondcontrol signal lines.
 7. The solid-state imaging device according toclaim 1, wherein a cross-sectional area of each of the plurality ofreadout connections is greater than a cross-sectional area of each ofthe plurality of control connections.
 8. The solid-state imaging deviceaccording to claim 1, wherein the control circuit is configured tooutput a plurality of the control signals that are provided to each ofthe plurality of pixels, and a length of a path of each of the pluralityof the control signals from the control circuit to each of the pluralityof pixels is different for each of the plurality of the control signals.